A clock reset generation circuit mounted on a semiconductor integrated circuit has functions generating a system clock supplied to respective function units inside a chip while using an oscillation clock as an input, and generating an internal reset supplied to the respective function units by receiving a reset request from internal or external. In a conventional clock reset generation circuit, an internal reset signal is asynchronously asserted by the reset request and so on from external.
However, it becomes necessary in recent years to assert the internal reset signal in synchronous with the system clock when the reset request from external is input under a state in which the system clock is supplied inside the chip. One of reasons is to keep data (to prevent data damage) stored in an on-chip RAM.
The assertion of the internal reset signal in synchronous with the system clock is generally performed by synchronizing the reset request from external by flip-flop, and by controlling the system clock by a gated clock buffer so that the clock does not become a noise by the assertion of the reset signal. (For example, refer to Japanese Laid-open Patent Publication No. 05-12455.)
However, there is a case when the system clock is not supplied to the clock reset generation circuit for a microcontroller depending on an operation state. In this case, it is impossible to correspond to the reset request from external only by the function asserting the internal reset signal in synchronization with the system clock. Accordingly, a mechanism becomes necessary switching between a case when the internal reset signal is synchronously asserted under the operation state when the system clock is supplied to the clock reset generation circuit and a case when the internal reset signal is asynchronously asserted under the operation state when the system clock is not supplied to the clock reset generation circuit.
The synchronization/asynchronization switching mechanism has to be able to surely assert the internal reset signal in accordance with the reset request from external even at a timing switching the synchronization and asynchronization in addition to prevent that glitch occurs at the switching timing. Besides, if a reset factor based on the reset request from external remains inside the clock reset generation circuit when the internal reset signal is negated, the internal reset signal is asserted by a subsequent supply of the system clock. Accordingly, it is desired that the reset factor based on the reset request from external does not remain inside the clock reset generation circuit when the internal reset signal is negated.